Manipulation In The Forest

Manipulation-In The Forest

Material:-
Background
Taylor Swift Png Image

Open PhotoScape, click "Editor" and stay on the ward "Home."
Open a photo Of The background of the forest
Brightness,Color>Deepen>Middle
Auto Level>High
Brightness,Color>Darken>High
Now Click On Object & Select The Girl Image & adjust It in the background
Click Photo+Objects & Click Ok
Filter>Film Effect>Cinema>High
Bloom>High
Brightness, Color> Color Enhancement>Middle

Result:-

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How to generate Digital Filter Coefficient and test the Filter in Matlab

This blog post shows how to generate a digital filter coefficient for a given input signal and then test the filter with impulse input signal.

Matlab has a two functions that are in a way inverse to each other. These function are prony and filter. The prony function generates Z transform of input signal with filter coefficient. The filter function generates output impulse response in response to given filter coefficients and input signal. Delta signal can be used with the filter coefficient to test the filter.

First generate some input signal like the following,

n = [0:50];
x = sin(2*pi*n/25);

Then use this signal x to determine filter coefficients a,b with the help of prony matlab function as follows,

[b,a] = prony(x,2,2);

The syntax of this function is,

[b,a] =prony{x,M,N)

where x is the input signal, M is the number of zeros and N is the number of poles

We can plot the input signal x as follows,

plot(n,x,*)

The plot is,

Now, we use the a,b coefficients generated above and check whether these filter coefficients generates the same output x in response to an input delta impulse.

Define delta signal to apply to the filter,

d = [1 zeros(1,50)];

Then apply this delta input to the filter using filter matlab function to get the filter response y,

y = filter(b,a,d);

Now plot y,

We see that when first x signal generated a and b coefficients and these coefficient were used for a filter we get the same signal back y for an input delta signal.

Indeed, we may plot both x and y on the same graph to see the result,

plot(n,x,*,n,y,o)

which gives,

So in this way we can use the prone and filter matlab functions to generate filter coefficients and later utilize them to build a digital filter. So these function are quite useful in Digital Signal Processing work using matlab.

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How to design Encoder using Verilog and VHDL

Encoder are used in communication system design to encode discrete data. They are found in source encoder, channel encoder as well as encryption of data. Decoder are used at the receiver to decode the encoded data. A simple encoder accepts 2^n inputs and outputs n bits, for example, if n is 3 then input is 8 bits. A truth table for 8x3 encoder is shown below.

This encoder truth table can be implemented using case, if or for statement. The case statement makes the code cleaner than with using if statement. The for statement finds more usefulness for larger encoder construct. 

Below are verilog and VHDL code using the case statements.

Encoder using case in VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity encoder is
    port(
    A : in unsigned(7 downto 0);
    Y : out unsigned(2 downto 0)
    );
end encoder;

architecture encoder_arch of encoder is
begin
    process(A)
    begin
        case A is
            when "00000001" => Y <= "000";
            when "00000010" => Y <= "001";
            when "00000100" => Y <= "000";
            when "00001000" => Y <= "001";
            when "00010000" => Y <= "000";
            when "00100000" => Y <= "001";
            when "01000000" => Y <= "000";
            when "10000000" => Y <= "001";
            when others => Y <= "XXX";
        end case;
    end process;
end encoder_arch;

Encoder using case in Verilog

 module encoder(A,Y);
    input [7:0] A;
    output [2:0] Y;
    reg [2:0] Y;
  
    always@(A)
        begin
            casex(A)
                8b00000001 : Y = 0;
                8b00000010 : Y = 1;
                8b00000100 : Y = 2;
                8b00001000 : Y = 3;
                8b00010000 : Y = 4;
                8b00100000 : Y = 5;
                8b01000000 : Y = 6;
                8b10000000 : Y = 7;
                default : Y = 3bX;
            endcase
        end
    endmodule

The verilog code is shorter than the VHDL code for this case statement.

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