How to design Encoder using Verilog and VHDL

Encoder are used in communication system design to encode discrete data. They are found in source encoder, channel encoder as well as encryption of data. Decoder are used at the receiver to decode the encoded data. A simple encoder accepts 2^n inputs and outputs n bits, for example, if n is 3 then input is 8 bits. A truth table for 8x3 encoder is shown below.

This encoder truth table can be implemented using case, if or for statement. The case statement makes the code cleaner than with using if statement. The for statement finds more usefulness for larger encoder construct. 

Below are verilog and VHDL code using the case statements.

Encoder using case in VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity encoder is
    port(
    A : in unsigned(7 downto 0);
    Y : out unsigned(2 downto 0)
    );
end encoder;

architecture encoder_arch of encoder is
begin
    process(A)
    begin
        case A is
            when "00000001" => Y <= "000";
            when "00000010" => Y <= "001";
            when "00000100" => Y <= "000";
            when "00001000" => Y <= "001";
            when "00010000" => Y <= "000";
            when "00100000" => Y <= "001";
            when "01000000" => Y <= "000";
            when "10000000" => Y <= "001";
            when others => Y <= "XXX";
        end case;
    end process;
end encoder_arch;

Encoder using case in Verilog

 module encoder(A,Y);
    input [7:0] A;
    output [2:0] Y;
    reg [2:0] Y;
  
    always@(A)
        begin
            casex(A)
                8b00000001 : Y = 0;
                8b00000010 : Y = 1;
                8b00000100 : Y = 2;
                8b00001000 : Y = 3;
                8b00010000 : Y = 4;
                8b00100000 : Y = 5;
                8b01000000 : Y = 6;
                8b10000000 : Y = 7;
                default : Y = 3bX;
            endcase
        end
    endmodule

The verilog code is shorter than the VHDL code for this case statement.

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